Monday, June 24, 2019

The working principle of the start-up circuit of AMD dual-bridge RS880 chip board.

The AMD RS880 set motherboard power-up circuit works as shown in figure 1.
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Figure 1 operating principle block diagram of AMD RS880 chipset motherboard boot circuit.

Stage 1: after the CMOS battery is installed on the main board, the positive electrode of the battery passes through R692 and D43 to generate VBAT to power the RTC circuit inside the South Bridge chip. VBAT gets the high level SB _ VBAT signal from the JCMOS jumper cap to the South Bridge chip, and resets the RTC circuit inside the South Bridge Chip. The South Bridge chip supplies power to the crystal oscillator and the crystal oscillator starts to produce the 32.768kHz frequency to the South Bridge chip. The RTC circuit inside the South Bridge chip begins to work and is used to save the CMOS settings.

Stage2: the ATX power supply is turned on 220V alternating current, and the ATX power supply is output 5VSB power supply. After the step-down circuit is converted into 3VDUAL, the standby power supply is provided for the North Bridge chip and the IO chip. The IO chip sends out RSMRST_IO signal to the South Bridge chip after internal delay to indicate that the standby voltage is normal. So far, standby circuit work is complete.

Stage 3: the short switch generates the PSIN signal to the 10 chip, the 10 chip outputs the PWRBTN# signal of the 3.3V-0V-3.3V jump through the internal logic conversion and requests the power on the South Bridge chip. When the North Bridge chip receives the power-on request signal and its standby condition is normal, 3.3V continuous high-level SLP_S3# is output to the IO chip through the internal logic conversion, indicating that the power-up is allowed. Finally, the IO chip outputs the sustained low level ATX _ PSON# signal through the internal conversion, and pulls down the green line of the ATX power supply to complete the power-up.

This article is from Allicdata Electronics Limited. Reprinted need to indicate the source.

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